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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 rev. c 06/20/05 is62wv1288all is62wv1288bll issi ? copyright ? 2005 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 128k x 8 low voltage, ultra low power cmos static ram features ? high-speed access time: 45ns, 55ns, 70ns cmos low power operation: 30 mw (typical) operating 15 w (typical) cmos standby ttl compatible interface levels single power supply: 1.65v--2.2v v dd (62wv1288all) 2.5v--3.6v v dd (62wv1288bll) fully static operation: no clock or refresh required three state outputs industrial temperature available lead-free available description the issi is62wv1288all / is62wv1288bll are high- speed, 1m bit static rams organized as 128k words by 8 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high- performance and low power consumption devices. when cs1 is high (deselected) or when cs2 is low (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs. the active low write enable ( we ) controls both writing and reading of the memory. the is62wv1288all and is62wv1288bll are packaged in the jedec standard 32-pin tsop (typei), stsop (typei), sop, and 36-pin mini bga. functional block diagram june 2005 a0-a16 cs1 oe we 128k x 8 memory array decoder column i/o control circuit gnd v dd i/o data circuit i/o0-i/o7 cs2
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? pin descriptions a0-a16 address inputs cs1 chip enable 1 input cs2 chip enable 2 input oe output enable input we write enable input i/o0-i/o7 input/output nc no connection v dd power gnd ground 36-pin mini bga (b) (6mm x 8mm) 32-pin tsop (type i) (t), 32-pin stsop (type i) (h) pin configuration 32-pin sop (q) 1 2 3 4 5 6 a b c d e f g h a0 i/o4 i/o5 gnd v dd i/o6 i/o7 a9 a1 a2 oe a10 cs2 we nc nc cs1 a11 a3 a4 a5 nc a16 a12 a6 a7 a15 a13 a8 i/o0 i/o1 v dd gnd i/o2 i/o3 a14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 we cs2 a15 v dd nc a16 a14 a12 a7 a6 a5 a4 oe a10 cs1 i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd v dd a15 cs2 we a13 a8 a9 a11 oe a10 cs 1 i/o7 i/o6 i/o5 i/o4 i/o3
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? dc electrical characteristics (over operating range) symbol parameter test conditions v dd min. max. unit v oh output high voltage i oh = -0.1 ma 1.65-2.2v 1.4 ? v i oh = -1 ma 2.5-3.6v 2.2 ? v v ol output low voltage i ol = 0.1 ma 1.65-2.2v ? 0.2 v i ol = 2.1 ma 2.5-3.6v ? 0.4 v v ih (2) input high voltage 1.65-2.2v 1.4 v dd + 0.2 v 2.5-3.6v 2.2 v dd + 0.3 v v il (1) input low voltage 1.65-2.2v ?0.2 0.4 v 2.5-3.6v ?0.2 0.6 v i li input leakage gnd v in v dd ?1 1 a i lo output leakage gnd v out v dd , outputs disabled ?1 1 a notes: 1. undershoot: ?1.0v for pulse width less than 10 ns. not 100% tested. 2. overshoot: v dd + 1.0v for pulse width less than 10 ns. not 100% tested. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ?0.2 to v dd +0.3 v v dd v dd related to gnd ?0.2 to +3.8 v t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range (v dd ) range ambient temperature is62wv1288all is62wv1288bll commercial 0c to +70c 1.65v - 2.2v 2.5v - 3.6v industrial ?40c to +85c 1.65v - 2.2v 2.5v - 3.6v truth table mode we we we we we cs1 cs1 cs1 cs1 cs1 cs2 oe oe oe oe oe i/o operation v dd current not selected x h x x high-z i sb 1 , i sb 2 (power-down) x x l x high-z i sb 1 , i sb 2 output disabled h l h h high-z i cc read h l h l d out i cc write l l h x d in i cc
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? ac test loads figure 1 figure 2 capacitance (1) symbol parameter cond itions max. unit c in input capacitance v in = 0v 8 pf c out input/output capacitance v out = 0v 10 pf note: 1. tested initially and after any design or process changes that may affect these parameters. ac test conditions parameter 62wv1288all 62wv1288bll (unit) (unit) input pulse level 0.4v to v dd -0.2v 0.4v to v dd -0.3v input rise and fall times 5 ns 5ns input and output timing v ref v ref and reference level output load see figures 1 and 2 see figures 1 and 2 1.65v - 2.2v 2.5v - 3.6v r1( ?) 3070 3070 r2( ?) 3150 3150 v ref 0.9v 1.5v v tm 1.8v 2.8v r1 30 pf including jig and scope r2 output vtm r1 5 pf including jig and scope r2 output vtm
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? power supply characteristics (1) (over operating range) 62wv1288all (1.65v - 2.2v) symbol parameter test conditions max. unit 70 ns i cc v dd dynamic operating v dd = max., com. 8 ma supply current i out = 0 ma, f = f max ind. 8 typ. (2) 5 i cc 1 operating supply v dd = max., com. 5 ma current i out = 0 ma, f = 0 ind. 5 i sb 1 ttl standby current v dd = max., com. 0.8 ma (ttl inputs) v in = v ih or v il ind. 0.8 cs1 = v ih , cs2 = v il , f = 1 mh z i sb 2 cmos standby v dd = max., com. 10 a current (cmos inputs) cs1 v dd ? 0.2v, ind. 10 cs2 0.2v, typ. (2) 5 v in v dd ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd =1.8v, t a =25 o c. not 100% tested. power supply characteristics (1) (over operating range) 62wv1288bll (2.5v - 3.6v) symbol parameter test conditions max. max. unit 45ns 55 ns i cc v dd dynamic operating v dd = max., com. 17 15 ma supply current i out = 0 ma, f = f max ind. 17 15 typ. (2) 12 10 i cc 1 operating supply v dd = max., com. 5 5 ma current i out = 0 ma, f = 0 ind. 5 5 i sb 1 ttl standby current v dd = max., com. 0.8 0.8 ma (ttl inputs) v in = v ih or v il ind. 0.8 0.8 cs1 = v ih , cs2 = v il , f = 1 mh z i sb 2 cmos standby v dd = max., com. 10 10 a current (cmos inputs) cs1 v dd ? 0.2v, ind. 10 10 cs2 0.2v, typ. (2) 55 v in v dd ? 0.2v, or v in 0.2v, f = 0 note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v dd =3.0v, t a =25 o c. not 100% tested.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? ac waveforms read cycle no. 1 (1,2) (address controlled) ( cs1 = oe = v il , cs2 = we = v ih ) data valid previous data valid t aa t oha t oha t rc d out address read cycle switching characteristics (1) (over operating range) 45 ns 55 ns 70 ns symbol parameter min. max. min. max. min. max. unit t rc read cycle time 45 ? 55 ? 70 ? ns t aa address access time ? 45 ? 55 ? 70 ns t oha output hold time 10 ? 10 ? 10 ? ns t acs1/ t acs2 cs1 /cs2 access time ? 45 ? 55 ? 70 ns t doe oe access time ? 20 ? 25 ? 35 ns t hzoe (2) oe to high-z output 0 15 0 20 0 25 ns t lzoe (2) oe to low-z output 5 ? 5 ? 5 ? ns t hzcs1/ t hzcs2 (2) cs1 /cs2 to high-z output 0 15 0 20 0 25 ns t lzcs1/ t lzcs2 (2) cs1 /cs2 to low-z output 5 ? 10 ? 10 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0 .4 to v dd -0.2v/v dd -0.3v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? ac waveforms read cycle no. 2 (1,3) ( cs1 , cs2, oe controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , cs1 = v il . cs2= we =v ih . 3. address is valid prior to or coincident with cs1 low and cs2 high transition. t rc t oha t aa t doe t lzoe t acs1/ t acs2 t lzcs1/ t lzcs2 t hzoe high-z data valid t hzcs address oe cs1 cs2 dout
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? write cycle switching characteristics (1,2) (over operating range) 45 ns 55 ns 70 ns symbol parameter min. max. min. max. min. max. unit t wc write cycle time 45 ? 55 ? 70 ? ns t scs1/ t scs2 cs1/ cs2 to write end 35 ? 45 ? 60 ? ns t aw address setup time to write end 35 ? 45 ? 60 ? ns t ha address hold from write end 0 ? 0 ? 0 ? ns t sa address setup time 0 ? 0 ? 0 ? ns t pwe we pulse width 35 ? 40 ? 50 ? ns t sd data setup to write end 20 ? 25 ? 30 ? ns t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 20 ? 20 ? 20 ns t lzwe (3) we high to low-z output 5 ? 5 ? 5 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9v/1.5v, input pulse levels of 0 .4v to v dd -0.2v/v dd -0.3v and output loading specified in figure 1. 2. the internal write time is defined by the overlap of cs1 low, cs2 high, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that termi nates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. ac waveforms write cycle no. 1 ( cs1 /cs2 controlled, oe = high or low ) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address cs1 cs2 we dout din
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? ac waveforms write cycle no. 2 ( we controlled: oe is high during write cycle) write cycle no. 3 ( we controlled: oe is low during write cycle) data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din data-in valid data undefined t wc t scs1 t scs2 t aw t ha t pwe t hzwe high-z t lzwe t sa t sd t hd address oe cs1 cs2 we dout din
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? data retention switching characteristics symbol parameter test condition min. max. unit v dr v dd for data retention see data retention waveform 1.2 3.6 v i dr data retention current v dd = 1.2v, cs1 v dd ? 0.2v ? 5 a t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ?ns data retention waveform ( cs1 cs1 cs1 cs1 cs1 controlled) data retention waveform (cs2 controlled) v dd cs1 v dd - 0.2v t sdr t rdr v dr cs1 gnd data retention mode v dd cs2 0.2v t sdr t rdr v dr cs2 gnd data retention mode
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 rev. c 06/20/05 is62wv1288all, is62wv1288bll issi ? ordering information is62wv1288all (1.65v - 2.2v) industrial range: -40c to +85c speed (ns) order part no. package 70 IS62WV1288ALL-70BI mini bga (6mm x 8mm) is62wv1288all-70hi stsop, type i is62wv1288bll (2.5v-3.6v) industrial range: -40c to +85c speed (ns) order part no. package 45 is62wv1288bll-45ti tsop, type i is62wv1288bll-45bi mini bga (6mm x 8mm) is62wv1288bll-45hi stsop, type i is62wv1288bll-45qi sop 55 is62wv1288bll-55ti tsop, type i is62wv1288bll-55tli t sop, type i, lead-free is62wv1288bll-55bi mini bga (6mm x 8mm) is62wv1288bll-55hi stsop, type i is62wv1288bll-55hli stsop, type i, lead-free is62wv1288bll-55qi sop is62wv1288bll-55qli sop, lead-free
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. e 01/15/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. mini ball grid array package code: b (36-pin) notes: 1. controlling dimensions are in millimeters. mbga - 6mm x 8mm millimeters inches sym. min. typ. max. min. typ. max. n0. leads 36 36 a 1.20 0.047 a1 0.24 0.30 0.009 0.012 a2 0.60 0.024 d 7.90 8.00 8.10 0.311 0.315 0.319 d1 5.25bsc 0.207bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 mbga - 8mm x 10mm millimeter inches sym. min. typ. max. min. typ. max. n0. leads 36 36 a 1.20 0.047 a1 0.24 0.30 0.009 0.012 a2 0.60 0.024 d 9.90 10.00 10.10 0.390 0.394 0.398 d1 5.25bsc .207bsc e 7.90 8.00 8.10 0.311 0.315 0.319 e1 3.75bsc 0.148bsc e 0.75bsc 0.030bsc b 0.30 0.35 0.40 0.012 0.014 0.016 seating plane a a1 a2 a b c d e f g h e e d1 e1 e d b (36x) top view bottom view 6 5 4 3 2 1 1 2 3 4 5 6 a b c d e f g h
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/13/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. 450-mil plastic sop package code: q (32-pin) d seating plane b e c 1 n e1 a1 a e l s millimeters inches symbol min. max. min. max. no. leads 32 a ? 3.00 ? 0.118 a1 0.10 ? 0.004 ? b 0.36 0.51 0.014 0.020 c 0.15 0.30 0.006 0.012 d 20.14 20.75 0.793 0.817 e 13.87 14.38 0.546 0.566 e1 11.18 11.43 0.440 0.450 e 1.27 bsc 0.050 bsc l 0.58 0.99 0.023 0.039 0 10 0 10 s ? 0.86 ? 0.034 notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
integrated silicon solution, inc. packaging information issi ? plastic stsop - 32 pins package code: h (type i) notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e do not include mold flash protru- sions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. plastic stsop (h - type i) millimeters inches symbol min max min max ref. std. n 32 a ? 1.25 ? 0.049 a1 0.05 ? 0.002 ? a2 0.95 1.05 0.037 0.041 b 0.17 0.23 0.007 0.009 c 0.14 0.16 0.0055 0.0063 d 13.20 13.60 0.520 0.535 d1 11.70 11.90 0.461 0.469 e 7.90 8.10 0.311 0.319 e 0.50 bsc 0.020 bsc l 0.30 0.70 0.012 0.028 s 0.28 typ. 0.011 typ. 0 5 0 5 pk13197h32 rev. b 04/21/03 d1 seating plane c d 1 n e s b a1 a a2 e l
packaging information issi ? integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. c 06/13/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. plastic tsop-type i package code: t (32-pin) d seating plane b e c 1 n e a1 a s h l notes: 1. controlling dimension: millimeters, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package. 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. millimeters inches symbol min. max. min. max. no. leads 32 a ? 1.20 ? 0.047 a1 0.05 0.25 0.002 0.010 b 0.17 0.23 0.007 0.009 c 0.12 0.17 0.005 0.007 d 7.90 8.10 0.311 0.319 e 18.30 18.50 0.720 0.728 h 19.80 20.20 0.780 0.795 e 0.50 bsc 0.020 bsc l 0.40 0.60 0.016 0.024 0 8 0 8 s 0.25 ref 0.010 ref

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